Electronic designs for large systems may include millions of gates and megabits of embedded memory. Of the tasks required for managing and optimizing electronic designs on a target device, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of computer aided design (CAD) or electronic design automation (EDA) tools to manage and optimize designs for a system. CAD tools perform the time-consuming tasks of synthesis, placement, and routing on a target device.
Registers in a system may be connected to a reset signal that operates to put the system into a known state during start up or after the occurrence of an error. The reset signal may be used to reset the system upon the occurrence of an event or after an amount of time has passed. Register resets, however, pose challenges for designing a system onto a target device. Challenges for asynchronous and synchronous resets include achieving timing closure when having to fan a reset signal out to a large number of destinations, and performing fitting with limited wiring resources allocated for resets while complying with clustering constraints associated with the resets. Asynchronous resets may further impose further challenges with sequential optimization issues. Sequential optimization algorithms used by CAD or EDA tools may bypass registers with asynchronous signals such as resets or loads. If the sequential optimizations are not bypassed, startup conditions created by the asynchronous reset are still maintained after retiming. Furthermore, logic may need to be packed into sequential elements without reset which require additional logic to be added to ensure correct startup behavior.